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general description the MAX3782 is a dual 1.25gbps data retiming and clock recovery transceiver. it interfaces 1.25gbps lvds data and clock to a 1.25gbps serial interface compati- ble with 1000base-sx/lx (ieee 802.3z-2000) standards, gbic, and small form-factor pluggable (sfp) module interface recommendations. the serial differential trans- mitter and receiver are pecl compatible using an ac- coupled cml interface with on-chip termination/bias resistors for superior forward and back terminations. the transmit path converts the lvds signaling to cml and retimes the serial data to a low-jitter reference clock. the transmitter section contains lvds buffers, fifo, clock multiplier, and cml output buffers. the transmitter accepts a single 1.25gbps serial-data channel and a 625mhz double-data-rate (ddr) clock that are compati- ble with ieee std 1596-1996 dc specifications. serial lvds data is clocked into the fifo on both edges of the 625mhz source-synchronous tclk. data is clocked out of the fifo using an internal 1.25ghz clock derived from a low-jitter 125mhz reference. serial data is then clocked out as differential cml. the receive path converts the cml signaling to lvds and locks on to the data stream to recover the source- synchronous clock (rclk). the receive section con- tains a cml input buffer, clock recovery circuit, and lvds output buffers. the receiver accepts a cml serial data stream. the clock recovery phase-locked loop (pll) locks on to the incoming serial data stream and generates a 625mhz lvds ddr clock. rclk edges are at the center of the ?ye?of rdat data. applications 1000base-sx/lx optical links gbic modules sfp fiber transceiver modules features 1000base-sx/lx, gbic, or sfp serial data conversion to/from 1.25gbps lvds serial data and ddr clock cml interface exceeds all pecl ac specifications for 1000base-sx/lx, gbic, or sfp serial data tx data retiming with <0.1ui total output jitter as per ieee802.3z rx data and clock recovery with 0.75ui jitter tolerance as per ieee802.3z on-chip forward and back termination using cml i/o and integrated termination/bias resistors pll lock status indicator system loopback jtag i/o scan for board-level testing MAX3782 dual 1.25gbps transceiver ________________________________________________________________ maxim integrated products 1 ordering information 19-2268; rev 2; 1/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code MAX3782ugk -5 c to +85 c 68 qfn-ep* g6800-4 * ep = exposed pad. typical application circuit appears at end of data sheet. rdat2+ tms-jtag rclk1+ qfn* top view gnd vcc6 refclk- refclk+ gnd tdat1- tdat1+ tclk1- tclk1+ vcc6 tdi-jtag gnd tclk-jtag rx1+ vcc5 vcc5 rx1- vcc5 gnd rx2- rx2+ gnd vcc5 vcctemp vcc4 tx2+ tx2- vcc4 gnd vcc4 tx1+ tx1- vcc4 vcc6 rxfil1 vcc2 gnd rclk2- rclk2+ vcc5 trst-jtag gnd rxfil2 vcc3 lock gnd rdat2- tdat2- tdat2+ tclk2- tclk2+ gnd gnd rclk1- vcc5 rdat1- rdat1+ tdo-jtag tempsens vcc1 txfil gnd gnd MAX3782 58 59 60 61 62 54 55 56 57 63 52 53 64 65 66 67 68 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 17 38 39 40 41 42 43 44 45 46 47 35 36 37 48 49 50 51 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 33 34 loopen reset the exposed pad of the qfn package must be soldered to ground for proper thermal and electrical operation of the MAX3782. * pin configuration
MAX3782 dual 1.25gbps transceiver 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = 3.0v to 3.6v, lvds differential load = 100 ? 1%, cml differential load = 100 ? 1%, t a = -5 c to +85 c, unless otherwise noted. typical values are at v cc = 3.3v and t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (vcc1, vcc2, vcc3, vcc4, vcc5, vcc6, vcctemp) ......................-0.5v to +4.0v lvds input and output voltage .................-0.5v to (v cc + 0.5v) lvttl input or output voltage...................-0.5v to (v cc + 0.5v) cml input voltage......................................-0.5v to (v cc + 0.5v) continuous cml output current ......................-10ma to +25ma momentary cml output voltage (duration <1min, +25 c)...............................0 to (v cc + 0.5v) tempsens, rxfil1, rxfil2, txfil voltage .........................................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85 c) 68-pin qfn (derate 38.5mw/ c above +85 c) ...............2.5w operating ambient temperature range ...............-5 c to +85 c operating junction temperature range .............-5 c to +150 c storage ambient temperature range...............-55 c to +150 c esd human body model (any pin) ....................................2000v parameter symbol conditions min typ max units supply current 440 620 ma power dissipation 1.45 2.23 w supply noise tolerance dc-500khz, single-ended refclk (note 1) 50 mv p-p lvttl inputs and outputs (except refclk) input high voltage 2.0 v input low voltage 0.8 v input high current -250 a input low current -500 a output high voltage (note 2) 2.4 v output low voltage (note 2) 0.4 v three-state enabled, 0.4v v out v cc -100 +100 output three-state current three-state enabled, gnd v out < 0.4v 400 a refclk inputs differential input amplitude refclk ac-coupled 200 2000 mv p-p single-ended input high voltage refclk- connected through 0.01f to gnd 2.0 v single-ended input low voltage refclk- connected through 0.01f to gnd 0.8 v refclk input high current 2.0v v in v cc 440 a refclk input low current gnd v in 0.8v -227 a cml inputs (note 3) differential input voltage range 802.3z and gbic compatible 370 2000 mv p-p common-mode voltage inputs open or ac-coupled v cc - 0.3 v input impedance (note 4) 85 100 115 ? cml outputs (note 3) differential output voltage 1100 2000 mv p-p output common-mode voltage v cc - 0.4 v differential output impedance (note 4) 85 100 115 ?
MAX3782 dual 1.25gbps transceiver _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = 3.0v to 3.6v, lvds differential load = 100 ? 1%, cml differential load = 100 ? 1%, t a = -5 c to +85 c, unless otherwise noted. typical values are at v cc = 3.3v and t a = +25 c.) parameter symbol conditions min typ max units lvds inputs input voltage range v i |v gpd | < 925mv 0 2000 mv differential input voltage |v id | |v gpd | < 925mv 150 500 mv differential input impedance r in 85 100 115 ? input common-mode current v os = 1.2v, inputs tied together 270 400 a lvds outputs differential output voltage |v od | 250 400 mv output high voltage v oh 1.475 v output low voltage v ol 0.925 v change in magnitude of differential output voltage for complementary states ? |v od | 25 mv output offset voltage v os 1.125 1.275 v change in magnitude of output offset voltage for complementary states ? |v os | 25 mv differential output impedance r od 80 100 120 ? short-circuit current short to supply or ground 40 ma note 1: supply noise tolerance is the amount of noise allowable on the power supply. the intent of this is to specify the conditions whereby the cml i/o jitter performance remains compliant with ieee802.3z jitter specifications. note 2: the lock output is open collector and requires a 10k ? pullup to v cc . tdo output load 11k ? to v cc or to gnd. note 3: cml differential signal amplitudes are specified as the total signal across the load (v+ - v-). cml inputs and outputs are designed to be ac-coupled. note 4: 100 ? is standard for sfp, nonstandard for ieee802.3z and gbic. ac electrical characteristics (v cc = 3.0v to 3.6v, lvds differential load = 100 ? 1%, cml differential load = 100 ? 1%, refclk = 125mhz, t a = -5 c to +85 c, unless otherwise noted. typical values are at v cc = 3.3v and t a = +25 c.) (note 5) parameter symbol conditions min typ max units jtag parameters clock frequency 15 mhz setup time data input to clock positive edge 15 7 ns hold time clock positive edge to data input 13 5 ns propagation delay clock negative edge to data output (c 20pf) 230ns tdo output rise time c 20pf, measured 20% to 80% 2 20 ns tdo output fall time c 20pf, measured 20% to 80% 1 20 ns tdo output three-state to active time c 20pf, measured as rise or fall time 1 30 ns
MAX3782 dual 1.25gbps transceiver 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (v cc = 3.0v to 3.6v, lvds differential load = 100 ? 1%, cml differential load = 100 ? 1%, refclk = 125mhz, t a = -5 c to +85 c, unless otherwise noted. typical values are at v cc = 3.3v and t a = +25 c.) (note 5) parameter symbol conditions min typ max units lock detect parameters assert time to assert, the tx and rx pll internal lock indicators must be high (lock achieved) for this period. 394 s deassert time to deassert, the tx or rx pll internal lock indicators must be low for this period 1053 s transmitter parameters tclk frequency 625 mhz refclk input rise/fall time single ended, 20% to 80% 2 ns transmitter latency from tdat to tx 5 ns lvds inputs accumulated phase error at tclk1 or tclk2 relative to refclk 1 ns setup time t su figure 1 100 42 ps hold time t h figure 1 100 42 ps cml outputs differential skew 25 ps tx output jitter, total (notes 6, 8) 32 73 ps p-p tx output jitter, deterministic (notes 6, 8) 9 20 ps p-p tx output jitter, random (notes 6, 8) 23 53 ps p-p receiver parameters (notes 7, 8) input data rate 1.25 gbps pll lock time k28.5 pattern applied to rx inputs, refclk must be applied and stable 1ms pattern = 2 7 - 1, differential skew = 0, 0.45ui p-p of data-dependent jitter 0.938 pattern = crpat, differential skew = 0ps, 0.45ui p-p of data-dependent jitter 0.885 pattern = crpat, differential skew = 218ps, 0.45ui p-p of data-dependent jitter 0.776 0.838 input jitter tolerance (note 9) p atter n = c jtp at, d i ffer enti al skew = 218p s, 0.248ui p-p of pulse-width distortion (note 10) 0.595 0.694 ui p-p differential skew tolerance 802.3z and gbic compliant 205 ps jitter generation 20 100 ps p-p receiver latency from rx to rdat 5 ns
MAX3782 dual 1.25gbps transceiver _______________________________________________________________________________________ 5 ac electrical characteristics (continued) (v cc = 3.0v to 3.6v, lvds differential load = 100 ? 1%, cml differential load = 100 ? 1%, refclk = 125mhz, t a = -5 c to +85 c, unless otherwise noted. typical values are at v cc = 3.3v and t a = +25 c.) (note 5) parameter symbol conditions min typ max units lvds outputs clock duty-cycle distortion variation of 50% crossing from ideal time -32 +32 ps deterministic jitter measured with k28.5 pattern at rdat_ outputs 850ps p-p edge speed t r , t f 20% to 80% 200 250 ps clock-to-data delay clk-q figure 2 268 400 532 ps reference clock requirements refclk frequency 125 mhz refclk frequency tolerance -100 +100 ppm refclk duty cycle 40 60 % 210 ps p-p f < 5khz, jitter assumed gaussian 15 ps rms refclk jitter f > 5khz, jitter is assumed deterministic, caused by power-supply noise and buffer jitter 20 ps p-p note 5: ac characteristics are guaranteed by design and characterization. note 6: tx output jitter, total, is the sum of both deterministic (20ps p-p max) and random (53ps p-p max at ber = 10 -12 ), as per ieee802.3z. measured with k28.5 pattern and one-pole 637khz highpass filter weighting. note 7: jitter test methods: these are described in the draft technical report by ansi t11.2/project 1230, document fc-mjs, fibre channel - methodologies for jitter specification. the maximum ber used to specify both fibre channel links, as well as ieee802.3z links is 10 -12 . note 8: jitter test conditions: the difference between the MAX3782 jitter specifications and the ieee802.3z standards (see table 1) represents the margin that must absorb all impairments such as jitter transfer from refclk, power-supply noise, and oscillator pulling (due to different tx and rx frequencies). note 9: input jitter tolerance is the total amount of high-frequency jitter at the inputs. total jitter = deterministic jitter (dj) + r andom jitter (rj) + 5mhz sinusoidal jitter (sj). random jitter = 2ps rms (35mui rms ). note 10: cjtpat is a unique pattern, which toggles between high transition-density sections to low transition-density sections at a rate within the loop bandwidth of a cdr. passing this signal through a band-limited channel results in data-dependent jitter (ddj) that has instantaneous phase jumps occurring at the rate of transition-density change. the phase vs. time looks like a low-frequency square wave. a 0.5ui p-p low-frequency square wave of jitter is the maximum that can be tolerated by an ideal cdr. in other words, 0.5ui p-p low-frequency square-wave jitter produces an equivalent stress as 1.0ui p-p high-fre- quency square-wave jitter.
MAX3782 dual 1.25gbps transceiver 6 _______________________________________________________________________________________ typical operating characteristics (v cc = 3.3v, t a = +25 c, unless otherwise noted.) 400 500 450 600 550 650 700 750 800 02030 10 40 50 60 70 80 supply current vs. temperature MAX3782 toc01 ambient temperature ( c) supply current (ma) -10 -6 -8 -2 -4 0 2 0.1 10k transmitter jitter transfer (reflck to tx_) MAX3782 toc02 jitter frequency (hz) jitter transfer (db) 10 1 100 1k -10 -6 -8 -2 -4 0 2 10k receiver jitter transfer (rx_ to rclk) MAX3782 toc03 jitter frequency (hz) jitter transfer (db) 10 1 100 1k 250 310 290 270 350 330 430 410 390 370 450 0 20 40 60 80 100 120 140 tempsens voltage vs. temperature MAX3782 toc04 junction temperature ( c) tempsens voltage (mv) 1 0.1 0.01 0.001 0.0001 0.1 10 1 100 1000 receiver power-supply rejection ratio MAX3782 toc05 noise frequency (mhz) added deterministic jitter (ps p-p /mv p-p ) 1 0.1 0.01 10k 100 1k 100k transmit clock synthesizer power-supply rejection ratio MAX3782 toc06 frequency (hz) added deterministic jitter (ps p-p /mv p-p ) without highpass weighting 637khz highpass weighting as per ieee802.3z method figure 2. definition of clock-to-data delay 1000mv p-p maximum input t h = 100ps t su = 100ps 300mv p-p minimum input differential amplitude center of rising or falling clock edge figure 1. lvds receiver input eye mask clk-q clk-q
MAX3782 dual 1.25gbps transceiver _______________________________________________________________________________________ 7 0 2 4 6 8 10 12 14 16 0 200 100 300 400 500 600 vco tx and vco rx2 pulling to vco rx1 MAX3782 toc07 frequency difference (ppm) added deterministic jitter (ps p-p ) 0 2 4 6 8 10 12 14 0 200 100 300 400 500 600 vco tx and vco rx1 pulling to vco rx2 MAX3782 toc08 frequency difference (ppm) added deterministic jitter (ps p-p ) 0 5 10 15 20 25 30 0 200 100 300 400 500 600 vco rx1 and vco rx2 pulling to vco tx MAX3782 toc09 frequency difference (ppm) added deterministic jitter (ps p-p ) without highpass weighting 637khz highpass weighting as per ieee802.3z method 100mv/ div input eye (dj = 0.4ui p-p , sj = 0.5ui p-p at 5mhz, 2 7 -1 prbs) MAX3782 toc10 200ps/div 100mv/ div recovered eye MAX3782 toc11 200ps/div 100 10 1 0.1 10k 100k 1m 10m sinusoidal jitter tolerance vs. frequency MAX3782 toc12 jitter frequency (hz) sinusoidal jitter amplitude (ui p-p ) with 0.4 ui p-p of data-dependent jitter present, pattern = 2 7 - 1 prbs 1 0.1 1 10 100 1000 10,000 5mhz jitter tolerance vs. input amplitude MAX3782 toc13 input amplitude (mv p-p ) sinusoidal jitter amplitude (ui p-p ) with 0.4ui p-p of data-dependent jitter present, pattern = 2 7 - 1 prbs typical operating characteristics (continued) (t a = +25 c, unless otherwise noted.) -2500 -1500 -2000 0 -500 -1000 1500 1000 500 2000 0 300 400 100 200 500 600 700 800 refclk to tclk accumulated phase-error tolerance MAX3782 toc14 phase at reset (ps) variation of delay after reset (ps) error-free operation refclk aligned to tclk
MAX3782 dual 1.25gbps transceiver 8 _______________________________________________________________________________________ pin description pin name function 1, 6, 13, 17, 21, 26, 31, 35, 43, 48, 51, 58, 62 gnd supply ground 2 tclk2+ transmitter positive clock input 2, lvds. input data is clocked on both the rising and falling edges of the 625mhz clock. 3 tclk2- transmitter negative clock input 2, lvds. input data is clocked on both the rising and falling edges of the 625mhz clock. 4 tdat2+ transmitter positive data input 2, lvds 5 tdat2- transmitter negative data input 2, lvds 7 trst-jtag jtag test reset input, lvttl. momentarily connect trst to gnd to reset jtag test circuitry. internally pulled high through 15k ? resistor. 8, 22, 25, 27, 30, 67 vcc5 3.3v supply for receiver digital functions and jtag circuitry 9 rclk2+ receiver positive clock output 2, lvds. output data is clocked on both the rising and falling edges of the 625mhz clock. 10 rclk2- receiver negative clock output 2, lvds. output data is clocked on both the rising and falling edges of the 625mhz clock. 11 rdat2+ receiver positive data output 2, lvds 12 rdat2- receiver negative data output 2, lvds 14 lock lock status indicator output, lvttl. this output goes high when the transmit pll and receiver plls are in lock. because this output is open-collector ttl, the lock pins from multiple MAX3782s can be connected in parallel to form a single lock signal. 15 vcc3 3.3v supply for rx2 receiver vco, analog receiver functions, and external loop-filter connection 16 rxfil2 rx2 receiver loop-filter connection. connect a 0.1f capacitor between rxfil2 and vcc3. 18 tdi-jtag jtag test data input, lvttl. internally pulled high through 15k ? resistor. 19 tms-jtag jtag test mode select input, lvttl. internally pulled high through 15k ? resistor. 20 tclk-jtag jtag test clock input, lvttl. internally pulled high through 15k ? resistor. 23 rx1+ receiver positive input 1, cml 24 rx1- receiver negative input 1, cml 28 rx2+ receiver positive input 2, cml 29 rx2- receiver negative input 2, cml 32 vcctemp 3.3v supply for tempsens. connect to ground to disable the temperature-sensing function. 33 tempsens junction temperature sensor output, analog. tempsens corresponds to the junction temperature of the die. leave open for normal use. 34 loopen loopback enable input, lvttl. force low to enable system loopback. internally pulled high through 15k ? . 36 vcc2 3.3v supply for rx1 receiver vco, analog receiver functions, and external loop-filter connection 37 rxfil1 rx1 receiver loop-filter connection. connect a 0.1f capacitor between rxfil1 and vcc2. 38, 53, 61 vcc6 3.3v supply for transmitter digital functions 39, 42, 44, 47 vcc4 3.3v supply for cml outputs
MAX3782 dual 1.25gbps transceiver _______________________________________________________________________________________ 9 pin description (continued) pin name function 40 tx1- transmitter negative output 1, cml 41 tx1+ transmitter positive output 1, cml 45 tx2- transmitter negative output 2, cml 46 tx2+ transmitter positive output 2, cml 49 txfil transmitter loop-filter connection. connect a 0.1f capacitor between txfil and vcc1. 50 vcc1 3.3v supply for transmitter vco, analog transmitter functions, and external loop-filter connection 52 reset reset input, lvttl. connect low for >80ns to reset fifo and receiver components. internally pulled high through 15k ? . 54 tclk1+ transmitter positive clock input 1, lvds. input data is clocked on both the rising and falling edges of the 625mhz clock. 55 tclk1- transmitter negative clock input 1, lvds. input data is clocked on both the rising and falling edges of the 625mhz clock. 56 tdat1+ transmitter positive data input 1, lvds 57 tdat1- transmitter negative data input 1, lvds 59 refclk+ reference clock positive input. see specification table for differential or single-ended use. 60 refclk- reference clock negative input. see specification table for differential or single-ended use. 63 rclk1+ receiver positive clock output 1, lvds. output data is clocked on both the rising and falling edges of the 625mhz clock. 64 rclk1- receiver negative clock output 1, lvds. output data is clocked on both the rising and falling edges of the 625mhz clock. 65 rdat1+ receiver positive data input 1, lvds 66 rdat1- receiver negative data input 1, lvds 68 tdo-jtag jtag test data output, three-state lvttl ep exposed pad s up p l y gr ound . the exp osed p ad m ust b e sol d er ed to the ci r cui t b oar d g r ound for p r op er ther m al and el ectr i cal p er for m ance. s ee e xp osed - p ad p ackag e. the m ax 3782 uses exp osed p ad var i ati on g6800- 4 i n the p ackag e outl i ne d r aw i ng .
MAX3782 dual 1.25gbps transceiver 10 ______________________________________________________________________________________ ttl lvds cml lvds ttl lvds lvds ttl lvds lvds lvds lvds pll clock multiplier dq fifo dq 625mhz ddr 625mhz ddr tx_lock (internal) refclk (internal) 1.25ghz cml cml d fifo dq q reset (internal) ttl ttl ttl ttl ttl jtag control circuitry divide by 2 0 1 qd pll clock recovery 625mhz ddr refclk (internal) lvds lvds cml divide by 2 0 1 qd pll clock recovery 625mhz ddr refclk (internal) reset (internal) tx_lock (internal) refclk tdat1 tclk1 tdat2 tclk2 rdat1 rclk1 lock rdat2 rclk2 reset loopen rxfil2 rx2 rxfil1 rx1 tx2 tx1 tdo-tjag tclk- jtag tdi- jtag tms- jtag txfil gnd v cc trst- jtag MAX3782 + - + - + - + - + - + - + - figure 3. functional diagram
detailed description the MAX3782 dual 1.25gbps transceiver is a data retimer and clock recovery device for 1000base-sx/lx, gbic, and sfp applications. in the transmitter, an inte- grated clock synthesizer generates a clean 1.25ghz clock. this clock is used with a fifo to retime the data before transmission. cml output buffers provide excel- lent performance with minimal external components. the receiver has two separate pll clock recovery cir- cuits, allowing independent recovery of each received data signal. the receiver has cml inputs, easing sys- tem design and decreasing component count. jtag functionality is included to help with board-level testing. a lock pin indicates the status of the internal plls. system loopback may be asserted with the loopen input. lvds inputs and outputs the MAX3782 lvds interface includes two differential data inputs at 1.25gbps, two half-rate differential clock inputs at 625mhz, two differential data outputs at 1.25gbps, and two half-rate differential clock outputs at 625mhz. the MAX3782 lvds-compatible interface is designed to work with the user s asics, minimize power dissipation, speed transition time, and improve noise immunity. the lvds outputs also have short- circuit protection in case of shorts to vcc or gnd. the lvds inputs must be dc-coupled for proper biasing. ac-coupling these inputs results in unreliable opera- tion. the lvds outputs are designed to drive 100 ? dif- ferential loads and are not designed to drive 50 ? to ground. pll clock multiplier the pll clock multiplier uses the 125mhz reference clock to synthesize the 1.25ghz clock that synchro- nizes the transmitter functions. the reference clock also aids frequency acquisition in the receiver. to achieve proper jitter performance and ber benchmarks, using a high-quality, low-jitter reference clock is critical. refclk inputs can be driven differentially or single ended. differential operation is recommended for its superior jitter performance and noise immunity. pll clock recovery both receive channels (rx1 and rx2) use plls to recover synchronous clocks from the incoming serial data. the recovered clocks are then used to retime the serial data. the typical loop bandwidth of the pll clock recovery circuits is 1.5mhz. cml inputs and outputs the cml inputs and outputs of the MAX3782 offer low power dissipation, excellent performance, and integrat- ed termination resistors. ac-coupling capacitors should be used for pecl and ieee802.3z compatibility. figure 4 shows interface examples. the cml output structure is shown in figure 5, and the cml input struc- ture is shown in figure 6. for more information, refer to MAX3782 dual 1.25gbps transceiver ______________________________________________________________________________________ 11 optional ecl or pecl 50 ? 50 ? bias cml w/ 100 ? back term z 0 = 100 ? cml to pecl optional cml w/ 100 ? back term z 0 = 100 ? cml to cml optional ecl or pecl cml w/ 100 ? end term cml w/ 100 ? end term z 0 = 100 ? pecl to cml 0.01 f 0.01 f 0.01 f 0.01 f current set current set optional 0.01 f 0.01 f figure 4. cml i/o interconnect examples
MAX3782 the applications note hfan-01.0, introduction to lvds, pecl, and cml . lock detection the lock output indicates the state of the transmitter and receiver plls. for lock detect to be asserted high, the transmitter and receiver internal lock indicators must be high for 394s. the internal lock signals go high once frequency lock has been achieved. for lock detect to be asserted low, either the transmitter or receiver internal lock indicators must be low for a mini- mum of 1053s. lock detect also is asserted low when the external reset pin is forced low. lock stays low for a minimum of 394s. for the lock detector to function properly, there must be data transitions at the rx1 and rx2 inputs and a valid reference clock input. note: the lock output is not an accurate indicator of signal presence at the receiver inputs. with no data input, the lock output can be high, low, or toggling. the output structure of the lock pin is shown in figure 7. reset input reset must be held low for a minimum of four reference clock cycles for it to be properly asserted. approximately 10ms or longer after power up, the reset input should be asserted low. reset resets the lock state and fifo clock logic. temperature sensor to help evaluate thermal performance, a temperature sensor is incorporated into the MAX3782. the tempera- ture sensor may be powered on or off regardless of the state of the rest of the chip. the vcctemp pin provides supply voltage for the temperature sensor circuit. the tempsens output is designed to output a voltage pro- portional to the die junction temperature (1mv per kelvin). the temperature of the die can be calculated as: tc v mv c mv c tempsens () ( ) ? 1 273 dual 1.25gbps transceiver 12 ______________________________________________________________________________________ MAX3782 r load = 10k ? v cc 100 ? lock figure 7. lock output structure MAX3782 32ma 50 ? 50 ? out+ out- v cc figure 5. cml output structure MAX3782 vcc 2k ? 50 ? 50 ? in+ in- gnd figure 6. cml input structure
applications information jitter budget example for optical link the MAX3782 outperforms ieee802.3z jitter specifica- tions. see figure 8 and table 1. jtag jtag functionality is compliant with ieee1149.1 specifi- cations. the bsdl file is available on request. table 2 provides jtag pin assignments. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground connec- tions short, and use multiple vias where possible. use controlled-impedance 50 ? transmission lines to interface with the MAX3782 high-speed inputs and outputs. place power-supply decoupling capacitors as close to v cc as possible. to reduce feedthrough, isolate the input signals from the output signals. MAX3782 dual 1.25gbps transceiver ______________________________________________________________________________________ 13 MAX3782 MAX3782 tp1 tp2 e/o o/e figure 8. optical link total jitter (ps p-p ) deterministic jitter (ps p-p ) compliance point ieee802.3z specification MAX3782 specification ieee802.3z specification MAX3782 specification 73 (max) 20 (max) tp1 192 32 (typ) 100 9 (typ) total jitter tolerance (ps p-p ) compliance point ieee802.3z specification MAX3782 specification 620 (min, crpat) tp2 600 670 (typ, crpat) table 1. comparison of ieee802.3z and MAX3782 jitter budget
MAX3782 dual 1.25gbps transceiver 14 ______________________________________________________________________________________ routing MAX3782 pin name boundary scan port name i/o type cell type in out lock lock open collector output observe and control 1 rx2+ rx2p cml input observe 2 rx2- rx2n cml input observe 2 rx1+ rx1p cml input observe 3 rx1- rx1n cml input observe 3 loopen loopen_bar lvttl input observe 4 tdat2+ tdat2p lvds input observe 5 tdat2- tdat2n lvds input observe 5 tclk2+ tck2p lvds input observe 6 tclk2- tck2n lvds input observe 6 tdat1+ tdat1p lvds input observe 7 tdat1- tdat1n lvds input observe 7 tclk1+ tck1p lvds input observe 8 tclk1- tck1n lvds input observe 8 tx1+ tx1p cml output observe and control 9 tx1- tx1n cml output observe and control 9 tx2+ tx2p cml output observe and control 10 tx2- tx2n cml output observe and control 10 reset reset_bar lvttl input observe 11 refclk+ refckp lvttl input observe 12 refclk- refckn lvttl input observe 12 rclk1+ rck1p lvds output observe and control 13 rclk1- rck1n lvds output observe and control 13 rdat1+ rdat1p lvds output observe and control 14 rdat1- rdat1n lvds output observe and control 14 rclk2+ rck2p lvds output observe and control 15 rclk2- rck2n lvds output observe and control 15 rdat2+ rdat2p lvds output observe and control 16 rdat2- rdat2n lvds output observe and control 16 jtag control pins tclk-jtag tck lvttl input tdi-jtag tdi lvttl input tdo-jtag tdo lvttl output tms-jtag tms lvttl input trst - jtag trst_bar lvttl input table 2. jtag pin assignments
exposed-pad package the exposed-pad, 68-pin qfn-ep incorporates features that provide a very low thermal-resistance path for heat removal from the ic. the ep and ep ring are electrical ground on the MAX3782 and must be soldered to the cir- cuit board for proper thermal and electrical performance. refer to hfan 08.10, thermal considerations of qfn and other exposed-pad packages, for more information. chip information transistor count: 14329 process: silicon bipolar MAX3782 dual 1.25gbps transceiver ______________________________________________________________________________________ 15 instruction jtag opcode action extest 000 b external boundary test mode sample/preload 001 b initialization for boundary test mode bypass 111 b connects bypass register between tdi and tdo idcode 010 b 32-bit device id register selected (see table 4) table 3. jtag instructions code version part no. manufacturer = maxim lsb binary 0001 b 0000 1110 1100 0110 b [ = 3782 base10 ] 00011001011 b [ ref: jedec jep106-i ] 1 b table 4. device identification code
MAX3782 dual 1.25gbps transceiver 16 ______________________________________________________________________________________ MAX3782 cmos asic 1.25gbps lvds tclk1 tdat1 tclk2 tdat2 rclk1 rdat1 rdat2 lock refclk tms-jtag tdi-tjag tclk-jtag rclk2 loopen reset 125mhz reference clock gbic or sfp optical module gbic or sfp optical module 1.25gbps gbic and ieee802.3z 1000base-sx/lx compatible vcc2 vcc3 vcc1 0.1 f 0.1 f 0.1 f tx1 rx1 tx2 rx2 rxfil1 rxfil2 txfil trst-jtag tdo-jtag typical application circuit
MAX3782 dual 1.25gbps transceiver ______________________________________________________________________________________ 17 68l qfn, 10x10x09,eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)
MAX3782 dual 1.25gbps transceiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)

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